Doped polysilicon via connecting polysilicon layers

ABSTRACT

The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.

BACKGROUND OF THE INVENTION

The invention relates to use of doped polycrystalline silicon(polysilicon) vias to provide electrical connection between verticallyseparate polysilicon layers, specifically polysilicon channel layers intransistors, gate electrodes, and other device elements.

When an electrical connection needs to be made between verticallyseparate layers in a semiconductor device, a vertical interconnect orvia is typically formed of a conductive material to connect them.

The typical method of formation is to form the lower layer to whichconnection is needed, then cover it with an insulating layer. Next ahole or void is excavated in the insulating layer, and the void isfilled with a conductive material, forming the via. The upper layer towhich conduction is needed is then formed above and in contact with thevia. Alternately, the via and the upper conductive layer can be formedof the same material, in a single deposition step.

Among the most common materials used for vias is tungsten. Tungsten viasor plugs are not compatible with all devices and materials, however.

There is a need, therefore, for other methods and materials to be usedfor forming vias in semiconductor structures.

SUMMARY OF THE PREFERRED EMBODIMENTS

The present invention is defined by the following claims, and nothing inthis section should be taken as a limitation on those claims. Ingeneral, the invention is directed to polysilicon vias used to provideelectrical connection to polysilicon structures.

A first aspect of the invention provides for a structure in asemiconductor device comprising a lower polysilicon layer; a polysiliconvia above the lower polysilicon layer, the polysilicon via having a topend and a bottom end, wherein the bottom end of the polysilicon via isin contact with the lower polysilicon layer; and an upper polysiliconlayer above the polysilicon via, wherein the top end of the polysiliconvia is in contact with the upper polysilicon layer.

Another aspect of the invention provides for a structure in asemiconductor device comprising: an upper channel layer in a firstdevice level of thin film transistors, the first device level at a firstheight above a substrate; and a polysilicon via in contact with theupper channel layer, wherein the upper channel layer is above thepolysilicon via.

A preferred embodiment of the invention provides for a structure in asemiconductor device comprising: a first channel layer, wherein thefirst channel layer is a portion of a first device level of thin filmtransistors, the first device level at a first height above a substrate;a second channel layer, wherein the second channel layer is a portion ofa second device level of thin film transistors, the second device levelat a second height above the substrate, wherein the second height isabove the first height; and a polysilicon via in contact with the firstchannel layer and in contact with the second channel layer.

Still another aspect of the invention provides for a structure in asemiconductor device comprising: a gate electrode at a first heightabove a substrate in an array of thin film transistors; a channel layerat a second height above the substrate in the array of thin filmtransistors, wherein the second height is above the first height; and apolysilicon via in contact with the gate electrode and in contact withthe channel layer.

Another preferred embodiment of the invention provides for a monolithicthree dimensional array of thin film transistors comprising: asubstrate; a first polysilicon layer at a first height above thesubstrate; a second polysilicon layer at a second height above thesubstrate, wherein the second height is above the first height; and apolysilicon via, wherein the polysilicon via is disposed between and incontact with the first polysilicon layer and the second polysiliconlayer, wherein the monolithic three dimensional array further comprisesat least a first device level and a second device level, the seconddevice level monolithically formed above the first device level.

A preferred embodiment of the invention provides for a method forforming a via structure in a semiconductor device, the methodcomprising: forming a polysilicon via through a dielectric material;planarizing a shared top surface of the polysilicon via and thedielectric material; and forming an upper polysilicon layer on and incontact with the polysilicon via.

Another aspect of the invention provides for a method for forming a viastructure to connect device levels in a monolithic three dimensionalarray, the method comprising: providing a substrate; forming a firstdevice level of thin film transistors at a first height above thesubstrate, the first device level comprising a first polysilicon layer;forming a polysilicon via above and in contact with the firstpolysilicon layer; and forming a second device level of thin filmtransistors at a second height above the substrate, wherein the secondheight is above the first height, the second device level comprising asecond polysilicon layer, wherein the second polysilicon layer is aboveand in contact with the polysilicon via.

Each of the aspects and embodiments of the invention described hereincan be used alone or in combination with one another.

The preferred aspects and embodiments will now be described withreference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 a and 1 b are cross-sectional views illustrate steps information of device levels connected by vias.

FIGS. 2 a and 2 b are cross-sectional views illustrating steps information of a tungsten via connecting two device levels.

FIG. 2 c is a cross-sectional view illustrating how a conductive barrierlayer renders the upper device level inoperative.

FIG. 3 a is a cross-sectional view illustrating formation of a structurehaving a polysilicon via formed according to the present inventionconnecting polysilicon layers in two device levels.

FIG. 3 b is a cross-sectional view of the structure of FIG. 3 a viewedat ninety degrees to the view of FIG. 3 a.

FIG. 3 c is a cross-sectional view of an alternative embodiment of thestructure of FIG. 3 a.

FIGS. 3 d and 3 e are cross-sectional views of the structure of FIGS. 3a and 3 b (along the same view as that shown in FIG. 3 b) showingcontinued fabrication of a via formed according to the presentinvention.

FIG. 3 f is a cross sectional view of a via formed according to thepresent invention connecting a gate electrode in a lower device level toa channel layer in an upper device level.

FIGS. 4 and 5 are cross-sectional views illustrating other forms thatvias according to the present invention may take.

DETAILED DESCRIPTION OF THE INVENTION

Tungsten, the most common choice to form vias to provide electricalconnection between vertically separate conductive layers, is notcompatible with all materials and structures.

An example of conductive layers formed at different heights above asubstrate in which vias formed according to the present invention mightadvantageously be used is found in Walker et al., U.S. patentapplication Ser. No. 10/335,089, “Programmable Memory Array StructureIncorporating Series-Connected Transistor Strings and Methods forFabrication and Operation of Same”, filed Dec. 31, 2002, assigned to theassignee of the present invention and hereby incorporated by referencein its entirety. Walker et al. describes formation of a monolithic threedimensional memory array of charge storage devices.

A first device level of an embodiment of Walker et al. is shown in FIG.1 a. A first channel layer 2 is formed of polysilicon. The term “channellayer” is used herein to mean a polysilicon layer in which one or morechannel regions are formed and in which at least one source, drain, orshared source/drain may be formed. In this embodiment, the first channellayer 2 comprises the channel regions 10 and shared sources and drains14 of a plurality of series-connected thin film transistors. Wordlines 6(shown in cross-section) form the gate electrode for each transistor. Atransistor 9 is formed wherever wordline 6 and channel layer 2intersect. In this embodiment an ONO stack 8 separates channel region 10from the gate electrode formed in wordline 6. Transistor 9 is a SONOSmemory cell.

A typical SONOS memory cell consists of (from the bottom up) a siliconchannel region, a tunneling oxide layer, a nitride charge storage layer,a blocking oxide layer, and a gate electrode, typically of silicon. Thesilicon-oxide-nitride-oxide-silicon stack gives the device its name.Other materials can replace some of the layers, however: Differentdielectric materials can be used for the tunneling, charge storage, andblocking dielectric layers, and the gate electrode need not be silicon.The term “SONOS-type device” will be understood to mean a device thatoperates the same way a SONOS device operates, storing charge in adielectric layer, but which is not necessarily limited to the materialsconventionally used in a SONOS device. Mahajani et al., U.S. patentapplication Ser. No. 10/270,127, “Thin Film Transistor with Metal OxideLayer and Method of Making Same,” filed Oct. 15, 2002, and herebyincorporated by references, describes formation and use of SONOS-typedevices made using dielectric materials other than silicon oxide andsilicon nitride.

Turning to FIG. 1 b, interlevel dielectric 16 is formed over firstdevice level 18. A second device level 20 of SONOS devices is formedabove interdielectric level 16, including second channel layers 22 andsecond wordlines 24. An ONO stack 21 separates second channel layers 22and second wordlines 24.

An electrical connection may be required between first channel layer 2and second channel layer 22. This can be done by forming via 26 of aconductive material. An electrical connection may also be requiredbetween a wordline 6 of first device level 18 and second channel layer22, for example by forming via 28 of a conductive material.

It will be understood by those skilled in the art that the locations ofvias 26 and 28 in FIG. 1 b are illustrative only. These vias could beformed at any point at which an electrical connection is desirable.

Most often in semiconductor devices, vias provide connections betweenmetal wiring layers, particularly to metal wiring formed above the via.For this purpose, vias are advantageously formed of tungsten or of someother conductive metal.

The embodiment shown in FIG. 1 b is unusual in that vias 26 and 28 mustprovide connectivity to an overlying polysilicon layer, or between twopolysilicon layers. It has been found that if, for example, vias 26 or28 are conventional vias formed of tungsten, problems may occur duringfabrication of an overlying polysilicon layer connecting to the via suchas channel layer 22.

FIG. 2 a shows a portion of the device of FIG. 1 b after formation offirst device level 18 and formation and planarization of interleveldielectric 16 above it. A void 30 is etched in interlevel dielectric 16,etching through the ONO stack 8 and exposing first channel layer 2. If aconventional tungsten via were to be formed, void 30 could be filledwith tungsten layer 32. A thin optional adhesion and barrier layer 34of, for example, titanium nitride may be deposited first, forming aliner, to improve the adhesion of tungsten layer 32 to dielectric 16.The overfill of tungsten layer 32 and barrier layer 34 are removed andthe surface planarized, for example by chemical mechanical polishing(CMP), to form finished tungsten via 36, shown in FIG. 2 b.

The difficulty may arise upon formation of the next layer, secondchannel layer 22. This layer would most typically be formed bydepositing silicon. Silicon is typically deposited on a surface byflowing a precursor gas containing silicon over the surface. Theprecursor gas most commonly used to deposit silicon is silane (SiH₄).

Silane reacts violently with tungsten, however, and the reaction maycause an undesirable reaction, creating “volcanoes” that will preventformation of a structurally and electrically intact channel layer. Anappropriate barrier of some sort between the tungsten and the silane isrequired, but such a barrier is difficult to form without complicatingthe process.

As shown in FIG. 2 c, a conductive barrier layer 38 of, for example,titanium nitride, could be formed first, separating tungsten via 36 andchannel layer 22 and allowing channel layer 22 to be formed. Thisbarrier layer 38, however, would act as a conductor, and would preventany portion of channel layer 22 from successfully operating as a channelregion of a transistor. (It will be recalled that a channel region mustbe semiconducting: It must be conductive when voltage is applied to thegate electrode and the transistor is on, but must not be conductive whenvoltage is not applied to the gate electrode and the transistor is off.The presence of conductive layer 38 would effectively cause anytransistors formed in channel layer 22 to be permanently on, regardlessof the voltage applied to the gate conductor of any transistor.)

The present invention solves this connectivity problem with a minimum ofprocess steps by forming a via of heavily doped polysilicon connectingto a top layer of polysilicon, or between polysilicon layers (such asvias 26 and 28 of FIG. 1 b).

Fabrication of two device levels of charge storage memory devicesconnected by polysilicon vias formed according to the present inventionwill be described here. These device levels can be two of many levelsformed in a monolithic three dimensional memory array such as the onedescribed in Walker et al. For brevity, not all of the details of Walkeret al. will be included, but it will be understood that no teaching ofWalker et al. is intended to be excluded.

For the sake of thoroughness, many details, including steps, processconditions, and materials, are provided. Those skilled in the art willappreciate that many of these details can be modified, added, or omittedwhile the results still fall within the scope of the invention.

Turning to FIG. 3 a, fabrication begins with any suitable substrate 100,preferably a monocrystalline silicon wafer. Circuitry, for exampledriver and sensing circuitry (not shown), and connections to thiscircuitry, may be formed in the substrate 100. A dielectric insulatinglayer 102 is formed over the substrate.

Channel layer 104 is formed of amorphous or polycrystallinesemiconductor on dielectric layer 102. Channel layer 104 is undoped orlightly doped with either p-type or n-type dopants. For clarity, thisdiscussion will assume this layer is lightly p-doped, though one skilledin the art will understand that the conductivity types can be reversed.

Channel layer 104 is formed by any conventional method. Semiconductorlayer 104 is preferably silicon, though other semiconductor materialscan be used. Gu, U.S. Pat. No. 6,713,371, “Large Grain Size PolysiliconFilms Formed by Nuclei-Induced Solid Phase Crystallization”; Gu et al.,U.S. patent application Ser. No. 10/681,509, “Uniform Seeding to ControlGrain and Defect Density of Crystallized Silicon for Use in Sub-MicronThin Film Transistors,” filed Oct. 7, 2003, and Gu et al., U.S. patentapplication Ser. No. ______, “Large-Grain P-Doped Polysilicon Films forUse in Thin Film Transistors,” filed Sep. 8, 2004, all assigned to theassignee of the present invention and hereby incorporated by reference,all describe methods to form polysilicon films with enhanced grain sizeand uniformity. Any of these methods may be advantageously used to formand crystallize semiconductor layer 104.

Channel layer 104 is patterned and etched using conventionalphotolithography techniques to form a plurality of substantiallyparallel stripes separated by gaps.

Next a charge storage region is formed on the channel layer stripes 104.In this example, the charge storage region is a tunneling dielectric 106of silicon dioxide, a charge storage dielectric 108 of silicon nitride,and a blocking dielectric 110 of silicon dioxide, forming ONO stack 112,though other dielectric materials could be used instead. Tunnelingdielectric 106 can be deposited or can be grown by oxidation of aportion of channel layer 104. Charge storage dielectric 108 and blockingoxide 110 are formed by any conventional method.

The wordlines, which will comprise the gate electrode for eachtransistor, are formed next. In this example, heavily doped p-typepolysilicon layer 114 is deposited by any suitable method. Next a layerof titanium is deposited, followed by a layer of titanium nitride. Ananneal follows, in which the titanium and titanium nitride layerscombine with a portion of underlying polysilicon layer 114 to formtitanium silicide layer 116. Finally heavily doped n-type polysiliconlayer 118 is deposited on titanium silicide layer 116.

FIG. 3 a shows the structure at this point. It will be seen that thewordline stack, including polysilicon layer 114, titanium silicide layer116, and polysilicon layer 118, is formed conformally, following thecontours of the channel layers 104 and the gaps between them.

Wordline stack layers 118, 116, and 114 are then etched to formwordlines, preferably extending substantially perpendicular to channellayer stripes 104. FIG. 3 b shows the same structure viewed at ninetydegrees to the view shown in FIG. 3 a, at a cross section along lineA-A′ in FIG. 3 a. In FIG. 3 b wordlines 120 are shown in cross section.

Walker et al. describe several possible ways of forming wordlines 120,including different layers and different dopant concentrations. What hasbeen described here is a preferred embodiment, but the other wordlineconfigurations described in Walker et al. could replace the onedescribed here.

Shared source/drain regions 122 are formed in channel layer stripes 104by doping using ion implantation, with wordlines 120 masking the channelregions 124 from implant. In some embodiments, the implant is performedin two steps: A first implant leaves the portions of channel layerstripes 104 not shielded by wordline 120 lightly doped. After formationof spacers 126, a second implant leaves the regions unshielded by thespacers 126 heavily doped. In preferred embodiments, the source/drainregions 122 are doped using an n-type dopant. The dopant concentrationachievable by ion implantation is typically between about 10¹⁵ atoms/cm³and about 10¹⁷ atoms/cm³. In general, dopant concentration ofsource/drain regions 122 is less than about 10¹⁷ atoms/cm³.

In an alternative embodiment shown in FIG. 3 c, wordlines 120 could beformed of a heavily doped polysilicon layer 114 only. In thisembodiment, ONO stack 112 is etched away between wordlines 120, exposingchannel layer stripe 104. After formation of spacers 126 and implant ofsource/drain regions 122, a silicide-forming metal, for example titaniumor cobalt, is deposited over the wordlines and the gaps between them. Ananneal causes creation of silicide 125 wherever the silicide-formingmetal overlies silicon (at the top of the wordlines 120 and onsource/drain regions 122) while unreacted metal remains over the spacersand between channel layer stripes 104. A wet etch strips away theunreacted metal, leaving silicide 125 formed on the wordlines 120 and onsource/drain regions 122.

FIG. 3 d illustrates the embodiment of FIG. 3 b as fabricationcontinues. First device level 128 is now complete. An interleveldielectric 130 is deposited over first device level 128, insulating itfrom the level to be formed above it. Interlevel dielectric 130 is thenplanarized, for example by CMP or etchback.

Next a via must be formed to provide an electrical connection betweenfirst device level 128 and the next device level (not yet fabricated.)The first step is to etch a void 132 through interlevel dielectric 130to the layer to which electric connectivity is desired. In this example,an electrical connection will be made to one of channel layer stripes104. Void 132 must etch through not only interlevel dielectric 130, butalso through the layers of ONO stack 112, exposing the top of channellayer stripe 104.

The portion of channel layer stripe 104 that is exposed by void 132, andto which contact will be made, is preferably heavily doped. It may be asource region, a drain region, a shared source/drain region, or aheavily doped region specifically formed to serve as a contact. Void 132is filled with very heavily doped polysilicon 134. FIG. 3 d illustratesthe structure at this point, including overfill of polysilicon 134.Polysilicon deposited by chemical vapor deposition is highly conformaland thus can fill even a very high-aspect ratio void. The polysilicon134 is preferably in situ doped, preferably having a dopantconcentration between about 10¹⁹ and about 10²¹ atoms/cm³, morepreferably between about 10²⁰ atoms/cm³ and about 10²¹ atoms/cm³. Ingeneral, dopant concentration is more than about 10¹⁹ atoms/cm³. In situdoping allows higher dopant concentrations than can be achieved by ionimplantation. Polysilicon 134 can be doped using either an n-type or ap-type dopant, but the dopant type should be the same dopant type as thepolysilicon regions to which contact is to be made to avoidunintentional formation of a diode. In this example, source/drainregions 122 were n-doped, so polysilicon 134 should also be n-doped.

Turning to FIG. 3 e, a planarization step is performed to remove theoverfill of polysilicon 134 and expose the top of interlevel dielectric130. This planarization can be done by CMP or etchback. A method toperform a planarizing etch of a conductive and a dielectric materialcreating a minimal step or no step is described in Raghuram et al., U.S.patent application Ser. No. 10/883,417, “Nonselective UnpatternedEtchback to Expose Buried Patterned Features,” filed Jun. 30, 2004 andhereby incorporated by reference. The planarizing etch of Raghuram etal. can be used.

Next a second device level 136 is formed, preferably using the sametechniques and materials used to form first device level 128. Seconddevice level 136 includes channel layer stripes 138, having source/drainregions 140. In the example shown, polysilicon via 134 provides anelectrical connection between a heavily doped region of channel layerstripe 138 of second device level 136 and a heavily doped region ofchannel layer stripe 104 of first device level 128. As noted earlier,the heavily doped region in channel layer stripe 138 where contact ismade by via 134 (in this example to a source/drain region 140) should bedoped using the same dopant type used to dope polysilicon via 134 andsource/drain region 122 in channel layer stripe 104 to avoid inadvertentformation of a diode.

Throughout this discussion, via 134 has been described as having beenformed of polysilicon. If preferred, some other semiconductor materialor semiconductor alloy, such as germanium or silicon-germanium, could beused instead.

Polysilicon via 134 is more heavily doped than the contact regions inchannel layer stripes 104 and 138 to which it connects. Further, becausepolysilicon via 134 was in situ doped, dopant atoms are distributedevenly throughout polysilicon via 134. This is in contrast tosource/drain regions 122 and 140, which were doped by ion implantation.As noted, in general, doping by ion implantation cannot achieve dopantconcentrations as high as those achieved by in situ doping.

In general, the dopant concentration of the via 134 is preferably atleast two orders of magnitude higher than the dopant concentration ofthe polysilicon layers above (channel layer stripe 138) and below(channel layer stripe 104) to which connection is made.

When polysilicon via 134 is exposed to high temperatures, either by ananneal or by subsequent thermal processing, dopants diffuse frompolysilicon via 134 to the contacted regions in the channel layerstripes 104 and 138, improving the electrical contact between them.

To generalize, then the present invention provides for a structure in asemiconductor device comprising a first channel layer, wherein the firstchannel layer is a portion of a first device level of thin filmtransistors, the first device level at a first height above a substrate;a second channel layer, wherein the second channel layer is a portion ofa second device level of thin film transistors, the second device levelat a second height above the substrate, wherein the second height isabove the first height; and a polysilicon via in contact with the firstchannel layer and in contact with the second channel layer.

As described, the structure of the present invention is formed by amethod, the method comprising 1) forming a polysilicon via through adielectric material 2) planarizing a shared top surface of thepolysilicon via and the dielectric material and 3) forming an upperpolysilicon layer on and in contact with the polysilicon via.

It may instead be desired to form an electrical connection betweenwordline 120 of the first device level 128 and channel layer stripe 138of second device level 136. Such a connection is formed in a similarway. As shown in FIG. 3 f, a first device level 128 is formed asdescribed, interlevel dielectric 130 is deposited, and a void 133 isetched through interlevel dielectric 130, exposing the top of wordline120. In this example, the top of wordline 120 is doped polysilicon layer118. (An alternative embodiment was described, shown in FIG. 3 c, inwhich the top of wordline 120 was a silicide 125. In other embodimentsit can be some other conductive material, such as a metal.) Void 133 isfilled with very heavily doped polysilicon 135. As when via 134 wasformed, via 135 should be heavily doped in situ polysilicon having thesame dopant type as the polysilicon layer or layers to which itconnects. Its dopant concentration is preferably between about 10¹⁹ andabout 10²¹ atoms/cm³, more preferably between about 10²⁰ atoms/cm³ andabout 10²¹ atoms/cm³.

To summarize, FIG. 3 f shows a gate electrode at a first height above asubstrate in an array of thin film transistors; a channel layer at asecond height above the substrate in the array of thin film transistors,wherein the second height is above the first height; and a polysiliconvia in contact with the gate electrode and in contact with the channellayer.

As shown, a polysilicon via formed according to the present inventionmay be connecting two polysilicon layers, one above and one below thevia; or it may be connecting a polysilicon layer above to a conductivelayer formed of some other material below. A polysilicon via formedaccording to the present invention could be used, for example, toconnect a polysilicon structure such as a channel layer above the via toa monocrystalline semiconductor substrate, such as a portion of amonocrystalline silicon wafer, below the via. Alternatively, such a viacould connect a polysilicon structure such as a channel layer above thevia to a metal layer, such as a metal wiring layer, below the via.

To summarize, the present invention is used to create a structure in asemiconductor device comprising a lower polysilicon layer; a polysiliconvia above the lower polysilicon layer, the polysilicon via having a topend and a bottom end, wherein the bottom end of the polysilicon via isin contact with the lower polysilicon layer; and an upper polysiliconlayer above the polysilicon via, wherein the top end of the polysiliconvia is in contact with the upper polysilicon layer. In some aspects ofthe invention, the structure comprises an upper channel layer in a firstdevice level of thin film transistors, the first device level at a firstheight above a substrate; and a polysilicon via in contact with theupper channel layer, wherein the upper channel layer is above thepolysilicon via.

The examples provided herein show a simple layer-to-layer connection ofadjacent device levels using a via having a simple, columnar shape. Manyother options are possible. Walker et al., for example, teaches othertypes of vias. The via V shown in FIG. 4, for example, connects fourchannel layer stripes on three different device levels. Only a portionof channel layer stripes CH 1, CH 2, CH 3, and CH 4 are shown; they allextend left-to-right across the page, as indicated by the arrows. Thevia V has a stair-step profile. Still more memory levels can beconnected, as shown in FIG. 5, which shows via V1 connecting threedevice levels, while V2, formed directly above it, connects anotherthree device levels. Many other via arrangements can be imagined,including any of those taught in Walker et al.

Monolithic three dimensional memory arrays are described in Johnson etal., U.S. Pat. No. 6,034,882, “Vertically stacked field programmablenonvolatile memory and method of fabrication”; Johnson, U.S. Pat. No.6,525,953, “Vertically stacked field programmable nonvolatile memory andmethod of fabrication”; Knall et al., U.S. Pat. No. 6,420,215, “ThreeDimensional Memory Array and Method of Fabrication”; Lee et al., U.S.patent application Ser. No. 09/927,648, “Dense Arrays and Charge StorageDevices, and Methods for Making Same,” filed Aug. 13, 2001; Herner, U.S.application Ser. No. 10/095962, “Silicide-Silicon Oxide-SemiconductorAntifuse Device and Method of Making,” filed Mar. 13, 2002; Vyvoda etal., U.S. patent application Ser. No. 10/185,507, “Electrically IsolatedPillars in Active Devices,” filed Jun. 27, 2002; Scheuerlein et al.,U.S. application Ser. No. 10/335,078, “Programmable Memory ArrayStructure Incorporating Series-Connected Transistor Strings and Methodsfor Fabrication and Operation of Same,” filed Dec. 31, 2002; Vyvoda,U.S. patent application Ser. No. 10/440,882, “Rail Schottky Device andMethod of Making”, filed May 19, 2003; and Cleeves et al., “Optimizationof Critical Dimensions and Pitch of Patterned Features in and Above aSubstrate,” U.S. patent application Ser. No. 10/728,451, filed Dec. 5,2003, all assigned to the assignee of the present invention and herebyincorporated by reference.

A monolithic three dimensional memory array is one in which multiplememory levels are formed above a single substrate, such as a wafer, withno intervening substrates. The layers forming one memory level aredeposited or grown directly over the layers of an existing level orlevels. In contrast, stacked memories have been constructed by formingmemory levels on separate substrates and adhering the memory levels atopeach other, as in Leedy, U.S. Pat. No. 5,915,167, “Three dimensionalstructure memory.” The substrates may be thinned or removed from thememory levels before bonding, but as the memory levels are initiallyformed over separate substrates, such memories are not true monolithicthree dimensional memory arrays.

The present invention has been described herein in the context of amonolithic three dimensional memory array formed above a substrate. Suchan array comprises at least a first device level formed at a firstheight above the substrate and a second device level formed at a secondheight different from the first height. Three, four, eight, or moredevice levels can be formed above the substrate in such a multilevelarray, vertically stacked one above another in a monolithic threedimensional memory array.

As appropriate, the methods and devices of the present invention can beused in any of the monolithic three dimensional memory arrays describedin any of the incorporated references.

Many other variations can be imagined. In the embodiments described, thetransistors were SONOS-type memory cells. The memory cells could be ofsome other type of charge storage cells, such as floating gate memorycells. The transistors could lack charge-storage regions and be logictransistors rather than memory cells. The transistors in the examplegiven were series-connected; clearly many other circuit arrangements arepossible.

Detailed methods of fabrication have been described herein, but anyother methods that form the same structures can be used while theresults fall within the scope of the invention.

The foregoing detailed description has described only a few of the manyforms that this invention can take. For this reason, this detaileddescription is intended by way of illustration, and not by way oflimitation. It is only the following claims, including all equivalents,which are intended to define the scope of this invention.

1. A structure in a semiconductor device comprising: a lower polysiliconlayer; a polysilicon via above the lower polysilicon layer, thepolysilicon via having a top end and a bottom end, wherein the bottomend of the polysilicon via is in contact with the lower polysiliconlayer; and an upper polysilicon layer above the polysilicon via, whereinthe top end of the polysilicon via is in contact with the upperpolysilicon layer.
 2. The structure of claim 1 wherein the lowerpolysilicon layer is a portion of a first channel layer of a first thinfilm transistor.
 3. The structure of claim 2 wherein the upperpolysilicon layer is a portion of a second channel layer of a secondthin film transistor.
 4. The structure of claim 3 wherein the firstchannel layer is a portion of a first device level formed at a firstheight above a substrate.
 5. The structure of claim 4 wherein thesubstrate comprises monocrystalline silicon.
 6. The structure of claim 4wherein the second channel layer is a portion of a second device levelformed at a second height above the substrate, wherein the second heightis above the first height.
 7. The structure of claim 6 wherein thesecond device level is monolithically formed above the first devicelevel in a monolithic three dimensional array.
 8. The structure of claim7 wherein the monolithic three dimensional array comprises a pluralityof memory cells.
 9. The structure of claim 8 wherein the plurality ofmemory cells comprise charge storage memory cells.
 10. The structure ofclaim 9 wherein the charge storage memory cells are SONOS-type memorycells.
 11. The structure of claim 1 wherein the upper polysilicon layeris a portion of a second channel layer of a second thin film transistor.12. The structure of claim 11 wherein the lower polysilicon layer is aportion of a gate electrode of a first transistor.
 13. The structure ofclaim 11 wherein the second thin film transistor is a memory cell. 14.The structure of claim 13 wherein the memory cell is a SONOS-type memorycell.
 15. The structure of claim 13 wherein the memory cell is afloating gate memory cell.
 16. The structure of claim 1 wherein thepolysilicon via has a first dopant concentration and the upperpolysilicon layer has a second dopant concentration, wherein the firstdopant concentration is at least two orders of magnitude higher than thesecond dopant concentration.
 17. The structure of claim 1 wherein thepolysilicon via has a first dopant concentration and the lowerpolysilicon layer has a second dopant concentration, wherein the firstdopant concentration is at least two orders of magnitude higher than thesecond dopant concentration.
 18. A structure in a semiconductor devicecomprising: an upper channel layer in a first device level of thin filmtransistors, the first device level at a first height above a substrate;and a polysilicon via in contact with the upper channel layer, whereinthe upper channel layer is above the polysilicon via.
 19. The structureof claim 18 wherein the polysilicon via is in situ doped.
 20. Thestructure of claim 19 wherein the polysilicon via has a first dopantconcentration greater than about 1×10¹⁹ atoms/cm³.
 21. The structure ofclaim 19 wherein the upper channel layer is not in situ doped.
 22. Thestructure of claim 21 wherein the upper channel layer is doped by ionimplantation.
 23. The structure of claim 22 wherein the upper channellayer has a second dopant concentration less than about 1×10¹⁷atoms/cm³.
 24. The structure of claim 21 wherein at least a seconddevice level of thin film transistors exists above the first devicelevel of thin film transistors.
 25. The structure of claim 24 whereinthe first and second device levels are vertically stacked in amonolithic three dimensional array.
 26. The structure of claim 25wherein the first device level of thin film transistors comprises aplurality of charge storage memory cells.
 27. The structure of claim 26wherein the plurality of charge storage memory cells comprise SONOS-typememory cells.
 28. The structure of claim 26 wherein the plurality ofcharge storage memory cells comprise floating gate memory cells.
 29. Thestructure of claim 18 wherein the substrate comprises monocrystallinesemiconductor.
 30. A structure in a semiconductor device comprising: afirst channel layer, wherein the first channel layer is a portion of afirst device level of thin film transistors, the first device level at afirst height above a substrate; a second channel layer, wherein thesecond channel layer is a portion of a second device level of thin filmtransistors, the second device level at a second height above thesubstrate, wherein the second height is above the first height; and apolysilicon via in contact with the first channel layer and in contactwith the second channel layer.
 31. The structure of claim 30 wherein thepolysilicon via is in situ doped.
 32. The structure of claim 31 whereinthe polysilicon via has a first dopant concentration greater than about1×10¹⁹ atoms/cm³.
 33. The structure of claim 31 wherein the secondchannel layer is not in situ doped.
 34. The structure of claim 33wherein the upper channel layer is doped by ion implantation.
 35. Thestructure of claim 34 wherein the second channel layer has a seconddopant concentration less than about 1×10¹⁷ atoms/cm³.
 36. The structureof claim 30 wherein the first and second device levels are verticallystacked in a monolithic three dimensional array.
 37. The structure ofclaim 36 wherein the first device level of thin film transistorscomprises a plurality of charge storage memory cells.
 38. The structureof claim 37 wherein the plurality of charge storage memory cellscomprises SONOS-type memory cells.
 39. The structure of claim 37 whereinthe plurality of charge storage memory cells comprises floating gatememory cells.
 40. The structure of claim 30 wherein the substratecomprises monocrystalline silicon.
 41. A structure in a semiconductordevice comprising: a gate electrode at a first height above a substratein an array of thin film transistors; a channel layer at a second heightabove the substrate in the array of thin film transistors, wherein thesecond height is above the first height; and a polysilicon via incontact with the gate electrode and in contact with the channel layer.42. The structure of claim 41 wherein the polysilicon via is disposedvertically between the gate electrode and the channel layer.
 43. Thestructure of claim 41 wherein the gate electrode comprises dopedpolysilicon.
 44. The structure of claim 41 wherein the channel layer isa portion of a first device level of thin film transistors formed at thesecond height.
 45. The structure of claim 44 wherein the first devicelevel of thin film transistors comprises a plurality of charge storagememory cells.
 46. The structure of claim 45 wherein the plurality ofcharge storage memory cells comprise SONOS-type memory cells.
 47. Thestructure of claim 45 wherein the plurality of charge storage memorycells comprise floating gate memory cells.
 48. The structure of claim 41wherein the substrate comprises monocrystalline silicon.
 49. Thestructure of claim 41 wherein the polysilicon via comprises in situdoped polysilicon.
 50. The structure of claim 49 wherein the polysiliconvia has a first dopant concentration greater than about 1×10¹⁹atoms/cm³.
 51. The structure of claim 49 wherein the channel layercomprises polysilicon doped by ion implantation.
 52. The structure ofclaim 51 wherein the channel layer has a first dopant concentration lessthan about 1×10¹⁷ atoms/cm³.
 53. A monolithic three dimensional array ofthin film transistors comprising: a substrate; a first polysilicon layerat a first height above the substrate; a second polysilicon layer at asecond height above the substrate, wherein the second height is abovethe first height; and a polysilicon via, wherein the polysilicon via isdisposed between and in contact with the first polysilicon layer and thesecond polysilicon layer, wherein the monolithic three dimensional arrayfurther comprises at least a first device level and a second devicelevel, the second device level monolithically formed above the firstdevice level.
 54. The monolithic three dimensional array of claim 53,wherein the second polysilicon layer is a portion of a second channellayer.
 55. The monolithic three dimensional array of claim 54 whereinthe second channel layer comprises a plurality of series-connected thinfilm transistors.
 56. The monolithic three dimensional array of claim 54wherein the first polysilicon layer is a portion of a first channellayer.
 57. The monolithic three dimensional array of claim 54 whereinthe first polysilicon layer is a portion of a gate electrode of a thinfilm transistor.
 58. The monolithic three dimensional array of claim 53wherein the substrate comprises monocrystalline silicon.
 59. Themonolithic three dimensional array of claim 53 wherein the array is anarray of memory cells.
 60. The monolithic three dimensional array ofclaim 59 wherein the array of memory cells comprises a plurality ofcharge storage memory cells.
 61. The monolithic three dimensional arrayof claim 60 wherein the charge storage memory cells are SONOS-typecells.
 62. The monolithic three dimensional array of claim 60 whereinthe charge storage memory cells are floating gate cells.
 63. A methodfor forming a via structure in a semiconductor device, the methodcomprising: forming a polysilicon via through a dielectric material;planarizing a shared top surface of the polysilicon via and thedielectric material; and forming an upper polysilicon layer on and incontact with the polysilicon via.
 64. The method of claim 63 wherein thestep of forming a polysilicon via comprises: depositing the dielectricmaterial; etching a void in the dielectric material; and depositingin-situ doped polysilicon in the void.
 65. The method of claim 64wherein the step of planarizing a shared top surface of the polysiliconvia and the dielectric material comprises a CMP step.
 66. The method ofclaim 64 wherein the step of planarizing a shared top surface of thepolysilicon via and the dielectric material comprises an etchback step.67. The method of claim 66 wherein the etchback step comprises a firststage etch and a second stage etch, wherein the first stage etch removesexcess polysilicon, and the second stage etch etches both polysiliconand the dielectric material.
 68. The method of claim 67 wherein thesecond stage etch has lower selectivity between polysilicon and thedielectric material than the first stage etch.
 69. The method of claim64 wherein the step of forming an upper polysilicon layer comprises:depositing a polysilicon film; patterning and etching the polysiliconfilm to form an channel layer; and doping a portion of the channel layerby ion implantation.
 70. The method of claim 63 further comprising,before the step of forming a polysilicon via, forming a lowerpolysilicon layer below the polysilicon via, wherein the lowerpolysilicon layer is in contact with the polysilicon via.
 71. The methodof claim 70 wherein the step of forming the lower polysilicon layercomprises: depositing a polysilicon film; patterning and etching thepolysilicon film to form an channel layer; and doping the channel layerby ion implantation.
 72. The method of claim 70 wherein the step offorming the lower polysilicon layer comprises: depositing a polysiliconfilm; and patterning and etching the polysilicon film to form a gateelectrode of a transistor.
 73. The method of claim 63 wherein the upperpolysilicon layer is a portion of a first device level of thin filmtransistors formed above a substrate.
 74. The method of claim 73 whereinat least a second device level of thin film transistors ismonolithically formed above the first device level.
 75. The method ofclaim 74 wherein the first device level of thin film transistorscomprises a plurality of charge storage memory cells.
 76. The method ofclaim 75 wherein the plurality of charge storage memory cells compriseSONOS-type memory cells.
 77. The method of claim 75 wherein theplurality of charge storage memory cells comprise floating gate memorycells.
 78. The method of claim 73 wherein the substrate comprisesmonocrystalline silicon.
 79. The method of claim 63 further comprisingannealing the polysilicon via and the upper polysilicon layer such thatdopant atoms diffuse from the polysilicon via to the upper polysiliconlayer.
 80. A method for forming a via structure to connect device levelsin a monolithic three dimensional array, the method comprising:providing a substrate; forming a first device level of thin filmtransistors at a first height above the substrate, the first devicelevel comprising a first polysilicon layer; forming a polysilicon viaabove and in contact with the first polysilicon layer; and forming asecond device level of thin film transistors at a second height abovethe substrate, wherein the second height is above the first height, thesecond device level comprising a second polysilicon layer, wherein thesecond polysilicon layer is above and in contact with the polysiliconvia.
 81. The method of claim 80 wherein the first polysilicon layer is agate electrode of a thin film transistor of the first device level ofthin film transistors.
 82. The method of claim 80 wherein the firstpolysilicon layer is a first channel layer of a thin film transistor ofthe first device level of thin film transistors.
 83. The method of claim80 wherein the monolithic three dimensional array of claim 68 is anarray of memory cells.
 84. The method of claim 83 wherein the memorycells comprise charge storage memory cells.
 85. The method of claim 84wherein the charge storage memory cells comprise SONOS-type memorycells.
 86. The method of claim 84 wherein the charge storage memorycells comprise floating gate memory cells.
 87. The method of claim 80wherein the step of forming a polysilicon via comprises: forming a layerof dielectric material; etching a void in the layer of dielectricmaterial; filling the void with in situ doped polysilicon; andplanarizing the dielectric material and the in situ doped polysilicon toform a shared top surface.
 88. The method of claim 80 wherein thesubstrate comprises monocrystalline silicon.